The present invention relates to a semiconductor device (or semiconductor integrated circuit device) and can be applied to, for example, a power semiconductor device such as a power MOSFET.
Japanese Patent Laid-Open No. 2004-119611 (Patent Document 1) relates to a vertical power MOSFET having a super junction. Patent Document 1 discloses the technology to prevent a reduction in breakdown voltage due to the charge balance with an N-type drift area, by controlling the concentration distribution in a P-type drift area so that the concentration lowers toward deeper positions.
Japanese Patent Laid-Open No. 2003-229569 (Patent Document 2) also relates to a vertical power MOSFET having a super junction in the same way as in Patent Document 1. Patent Document 2 discloses the technology to perform embedded epitaxial growth at temperature not less than 800 degrees Celsius and not more than 1,000 degrees Celsius and at pressure not less than 1333.22 pascals and not more than 13332.2 pascals, by somewhat inclining the trench so as to leave no voids and by using dichlorosilane as a source gas.
Japanese Patent Laid-Open No. 2011-216587 (Patent Document 3) or US Patent Publication No. 2011-241111 (Patent Document 4) corresponding thereto also relates to a vertical power MOSFET having a super junction in the same way as in Patent Documents 1 and 2. Patent Document 3 and Patent Document 4 disclose the technology to make the concentration larger toward the surface side by forming a substrate side N-type epitaxial layer into a multilayer structure in order to compensate for the loss of charge balance resulting from the spread due to thermal treatment of the P-type drift area.